We are more or less familiar with the presence of mobile devices these days that sport dual-core and quad-core, and in some cases, octa-core chipsets, but what about this new prototype from the brains over at MIT? They have apparently come up with a 36-core computing chip that will make use of a system known as ‘network-on-a-chip’, allowing data to pass between cores in a far faster and more efficient manner compared the the traditional bus layouts that are in use at the moment.
While a standard multi-core processor will send all of its data through a single wire, allowing only a solitary core to communicate at a time, which means a growth in the number of cores would see these cores meeting a bottleneck as they wait for their turn to access to the bus to transfer data.
MIT’s latest prototype ‘network-on-a-chip’ design will see a paradigm shift introduced, as the cores have been arranged in a tiled grid layout, being hooked up directly to adjacent cores. This layout enables data to travel across the chip across various paths in order to skip cores that are currently occupied with processing work, or congested. At the end, it allows the entire processor to operate a whole lot more efficiently.