IBM today announced that it has developed an industry-first process with partners Samsung and Globalfoundries to manufacture silicon nanosheet transistors for 5 nanometer chips. It has been able to do this in less than two years after developing a 7nm test node chip with 20 billion transistors. The latest process enables the company to cram 30 billion transistors on a chip the size of a fingernail. IBM is going to provide the details of this process at the 2017 Symposia on VLSI Technology and Circuits Conference in Kyoto, Japan.
The method used for etching the chip was the same extreme ultraviolet lithography (EUV) that was used for the 7nm chip. However, for this process, the FinFET processor design was set aside in favor of silicon nanosheets.
This change enables individual switches to be fine-tuned so that their performance can be optimized even though they have been crammed into a fingernail-sized space. IBM says that the resulting increase in performance will help advance cognitive computing, the Internet of Things, and other cloud-based data-intensive applications.
The power savings may also enable batteries in smartphones and other devices to last up to three times longer than they do right now. That being said, it’s going to be a while before devices with 5nm chips hit the market.
We’ve yet to see devices with 7nm chips as they’re not expected to arrive before 2018 at the very least. What this does tell us that we still have a long way to go before being concerned about device performance hitting a peak.